1. Field of the Invention
The present invention relates to a data transmission system, and more particularly to a data transmission system for performing digital transmission of data.
2. Description of the Related Art
As LSI chips become larger in capacity, more highly integrated, and faster in operation, the amount of information handled by a single LSI chip is enormous and the amount of data inputted to and outputted from the LSI chip is also large. In order to transfer signals through a limited number of terminals on LSI chips to input and output the increased amount of data, it is necessary to provide efficient interfacing between LSI chips.
For efficiently transmitting and receiving data between LSI chips, it is the customary practice for the transmitting circuit to convert the data from parallel format to serial format for transmission over a reduced number of signal lines and for the receiving circuit to convert the received serial data back to the parallel data for reproduction of the data.
For example, data of 622.08 Mbps is processed at 77.76 Mbps×8 in an LSI chip, converted from parallel format to serial format at a ratio of 8:1 for being outputted from the LSI chip, and transmitted at 622.08 Mbps. The receiving circuit converts the received data from serial format to parallel format, obtaining the original parallel data.
The above conventional process of transmitting data between LSI chips is disadvantageous in that it occasionally happens for the bit sequence that is transmitted from the transmitting circuit to fail to be restored with accuracy.
FIGS. 11 and 12 of the accompanying drawings are illustrative of the above problem of the conventional process of transmitting data between LSI chips. A sending LSI chip 100 has a parallel/serial converter 101, and a receiving LSI chip 200 has a serial/parallel converter 201. One-bit data transmission is performed between the parallel/serial converter 101 and the serial/parallel converter 201.
The parallel/serial converter 101 has input terminals Pi1 through Pi8 supplied with respective parallel transmission data D1 through D8 of 77.76 Mbps. The parallel/serial converter 101 converts the transmission data D1 through D8 into serial data of 622.08 Mbps and outputs the serial data.
The serial/parallel converter 201 receives the serial data transmitted from the sending LSI chip 100, and converts the received serial data into parallel data and outputs data of 77.76 Mbps×8 from respective output terminals Po1 through Po8 thereof.
As shown in FIG. 11, the data D1 through D8 supplied to the respective input terminals Pi1 through Pi8 of the parallel/serial converter 101 should be outputted from the respective output terminals Po1 through Po8 of the serial/parallel converter 201.
However, as shown in FIG. 12, the data D4 to be outputted from the output terminal Po4 is outputted from the output terminal Po1, and the data D5 through D8, D1 through D3 are outputted respectively from the output terminals Po2 through Po8. The bit sequence is thus not restored with accuracy at the receiving LSI chip unless there is information indicative of a break in the serial data.
If the amount of data to be transmitted is too large, then since it cannot be transmitted over a single serial signal line, a plurality of signal lines are used to transmit serial data parallel to each other. This transmission scheme suffers, in addition to the above drawback, a problem in that because the serial data transmitted parallel to each other are subject to different propagation delays, the bit sequence of the parallel data reproduced at the receiving LSI chip tends to undergo a phase shift.